Cloud native EDA tools & pre-optimized hardware platforms
Join us for an exclusive and exciting opportunity to participate in an interactive forum where you'll discover the latest updates to 17³Ô¹Ï' cutting-edge mask synthesis products. You'll gain invaluable insights into the current challenges and solutions for advanced imaging from industry leaders specializing in High NA EUV, advanced 3D simulations, TCAD solutions for mask synthesis, verification, and the latest AI and GPU applications for computational lithography. Don't miss out on this chance to hear from the best in the business! Register now to secure your spot at this must-attend virtual event.
Kevin Lucas?, Sr. Architect, Applications Engineering, 17³Ô¹Ï
Thuc Dam, Director, Applications Engineering, 17³Ô¹Ï
Victor Moroz, Fellow, R&D Engineering, 17³Ô¹Ï
Uli Klostermann, Director, Applications Engineering, 17³Ô¹Ï
WooJoo Sim, Sr. Manager, R&D Engineering, 17³Ô¹Ï
Kostas Adam
VP of Engineering
17³Ô¹Ï
Tuesday, June 3, 2025
8:00 a.m. CEST | 11:30 a.m. IST | 2:00 p.m. CST | 3:00 p.m. JST
Tuesday, June 3, 2025
8:15 a.m. CEST | 11:45 a.m. IST | 2:15 p.m. CST | 3:15 p.m. JST
In the last year anamorphic HighNA EUV lithography has become a reality. HighNA EUV scanners are exposing wafers for process and mask synthesis learning at development fabs on three continents with more expected online soon. Leading companies are also actively working on early physical design rules, memory/logic cells and place/route methods for HighNA EUV processes including the significant two-mask stitching challenges. Therefore, there is a strong need for design to wafer, stitching-aware, HighNA EUV layout and mask optimization software. 17³Ô¹Ï has been working closely on HighNA EUV with IMEC, equipment suppliers, resist suppliers, leading fabs and physical design groups for several years. In this presentation we provide a detailed overview of 17³Ô¹Ï¡¯ HighNA EUV layout design, mask and wafer optimization flow and methods. We will provide examples of these methods applied to realistic physical designs, for different mask and wafer process options. We will also provide insight into how we see our flows and the general HighNA EUV lithography industry needs evolving.
Kevin Lucas
Sr. Architect, Applications Engineering
17³Ô¹Ï
Thuc Dam
Director, Applications Engineering
17³Ô¹Ï
Tuesday, June 3, 2025
8:45 a.m. CEST | 12:15 p.m. IST | 2:45 p.m. CST | 3:45 p.m. JST
The global demand for advanced semiconductors is surging, driven by the need for increased computing power for AI and big data analytics, consumer expectations for smaller and more efficient devices, and the requirements of communication and autonomous vehicles for faster data processing with lower latency. This is driving the relentless pursuit of Moore's Law to push the boundaries of transistor density and is accelerating lithography manufacturing complexities, thereby increasing the computational resources needed for computational lithography.
Applications like OPC and ILT can require thousands of cores to complete a single mask layer, and the demand for rigorous S-Litho lithography simulations is growing to support larger areas and advanced 3D simulations. To meet these computational challenges, 17³Ô¹Ï partnered with NVIDIA and TSMC to harness the massive parallel processing capabilities of GPUs. This collaboration is accelerating computational lithography, enabling faster mask synthesis and supporting the development of new process technologies. This talk will present the latest advancements that have been made to accelerate computational lithography to enable faster time to market for our customers and their new products.
Tuesday, June 3, 2025
9:15 a.m. CEST | 12:45 p.m. IST | 3:15 p.m. CST | 4:15 p.m. JST
Silicon chips contain many non-silicon layers and patterns, like metals and dielectrics that have distinctly different thermal expansion and shrinkage from silicon. Such differences in mechanical properties often lead to pattern-induced stress that can be intentional for stress engineering or unintentional. Historically, thick silicon wafers successfully resisted pattern induced stress and kept it from introducing considerable pattern deformation. However, recent introduction of chiplets changed this delicate balance, and stressed patterns started deforming the thin chiplets, which disrupts alignment of the deformed pattern and subsequent lithography masks. We demonstrate that TCAD stress analysis tools like Sentaurus Interconnect can perform accurate stress analysis for a given set of patterns and material properties. Bringing pattern deformation map from Sentaurus Interconnect into OPC tools like Proteus enables it to correct the next mask to match the underlying deformed pattern and improve manufacturability of chiplets.
Victor Moroz
Fellow, R&D Engineering
17³Ô¹Ï
Uli Klostermann
Director, Applications Engineering
17³Ô¹Ï
Tuesday, June 3, 2025
9:45 a.m. CEST | 1:15 p.m. IST | 3:45 p.m. CST | 4:45 p.m. JST
The continuous scaling of logic and memory devices to ever smaller dimensions is driving the need for improved and cost-efficient technologies. While low NA EUV lithography is deployed for the most advanced nodes to print at the smallest dimensions, DUV lithography at ArF wavelength is still being pushed well below a k1=0.28 (~ pitch 80nm) to improve cost-of-ownership. In both cases, EUV and DUV, non-ideal resist shapes lead to post-etch defects after resist etch transfer. Hence, the accurate prediction of Resist 3 Dimension Profiles (R3D), including resist thickness, is crucial to detect and correct weak pattern failures.
Simultaneously, the number and complexity of integrated (metal) layers are growing to meet the functional requirements for next-generation logic products (e.g. GPU, Vertical 3D Devices). Despite CMP processes in place, there are imperfections in the layer planarization, causing topographically induced challenges such as reduced depth of focus or CD skew. A topographic-aware compact model (T3D) will be presented, which can be used during mask synthesis (verification, correction) to account for these non-planarity challenges.
Tuesday, June 3, 2024
10:15 a.m. CEST | 1:45 p.m. IST | 4:15 p.m. CST | 5:15 p.m. JST
AI is increasingly being utilized in various aspects of computational lithography, expanding its application across process development and mask synthesis. To leverage AI technology to tape-out advanced node layers consisting of diverse layout patterns and process conditions, it is essential to apply different AI techniques tailored to the specific data types and objectives. These techniques are enabling AI solutions for pattern analytics, lithography simulation, and mask synthesis to outperform traditional methods, based on metrics suited to each application's unique characteristics.? Optimizing illumination source shapes and ILT recipes through reinforced learning has led to faster optimizations and higher-quality results for practical applications.? The solutions for pattern analytics and pattern generation are progressing in how they represent and manage existing pattern data while also creating new patterns that make AI applications more efficient and robust. Additionally, the advancements in generative AI technology significantly improve training efforts by reducing required patterns and process condition data through pre-training a model that can be generalized to different layers. In this talk, we'll showcase examples of these AI solutions in action across different tasks, sharing recent insights on improving accuracy and speed, ultimately making the tape-out of critical layers in advanced nodes more feasible and predictable.
WooJoo Sim
Sr. Manager, R&D Engineering
17³Ô¹Ï
Kostas Adam
VP of Engineering
17³Ô¹Ï
Kostas Adam leads 17³Ô¹Ï R&D and Product Engineering for the Mask 17³Ô¹Ï group. Prior to that, he was with Siemens EDA (known as Mentor Graphics until the 2017 acquisition by Siemens) for more than 20 years. He has worked in the Calibre OPC product line, in roles ranging in the early years from individual contributor to most recently the VP of engineering for all Mask Synthesis products of Calibre. Kostas has a PhD degree in EECS from UC Berkeley.
Kevin Lucas
Sr. Architect, Applications Engineering
17³Ô¹Ï
Kevin Lucas received a Ph.D. in E.E. from Carnegie Mellon Univ. with a thesis on rigorous lithography simulation. ?He then joined Motorola Semiconductor where he worked on OPC, lithography simulation and design rules with partners including IMEC, AMD, TSMC, ST, Phillips and IBM. He joined 17³Ô¹Ï in 2006 where he is a Senior Architect working on cross-functional High-NA EUV and Mask Error Correction flows.? He is a Fellow of SPIE and has ~200 publications in the field of optical lithography.
Thuc Dam
Director, Applications Engineering
17³Ô¹Ï
Thuc Dam holds a PhD in applied organic chemistry from UTD. He has worked in semiconductor field for 24 years with 30+ publications and 2 patents, and has previously been employed in technical and managerial roles at Intel and Luminescent Inc. His innovations in mask process development, ILT, SMO, and DRE have contributed extensively to the computational lithography domain. He is growing his experience in DTCO, AR/VR and EUV. He is currently the Director of Applications Engineering for the ILT, PLRC & SMO groups at 17³Ô¹Ï.
Victor Moroz
Fellow, R&D Engineering
17³Ô¹Ï
Dr. Victor Moroz is a 17³Ô¹Ï Fellow, engaged in a variety of projects on modeling Design-Technology Co-Optimization, FinFETs, gate-all-around transistors, stress engineering, 3D ICs, transistor scaling, cryogenic devices, Middle-Of-Line and Back-End-Of-Line resistance and capacitance, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters, a 100+ technical papers and over 300 US and international patents. Victor has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, EDTM, and ESSDERC, including serving as a Technical Chair of SISPAD 2018 and a max term Editor of IEEE Electron Device Letters.
Uli Klostermann
Director, Applications Engineering
17³Ô¹Ï
Dr. Uli Klostermann, received his PhD in Physics for his work on the patterning and characterization of nanometer sized magnetic tunnel junctions (MRAM). Before joining 17³Ô¹Ï, he worked in various positions in the technology development for next generation MRAM devices in the MRAM Development Alliance IBM/Infineon in US and later France and Germany. After joining 17³Ô¹Ï 2008, he focused on ensuring technology leadership for S-Litho in collaboration with our RnD team. He has initiated or contributed to numerous innovations, patents and publications in the fields of MRAM technology and lithographic simulations.
WooJoo Sim
Sr. Manager, R&D Engineering
17³Ô¹Ï
WooJoo is a Senior Manager of R&D at 17³Ô¹Ï, specializing in AI solutions for lithography and Optical Proximity Correction (OPC). His journey began with a Ph.D. at POSTECH, studying string theory. He then worked at Samsung Electronics on OPC, inspired by AlphaGo to delve into artificial intelligence. As a visiting scholar at the University of Michigan, he studied deep learning OPC and design optimization. He led the development of Samsung's in-house OPC software, applying deep learning techniques to enhance performance. WooJoo also worked at Standigm, an AI drug discovery company, before returning to the OPC field at 17³Ô¹Ï, aiming to expand its applications.