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Since the initial attempt to build a digital computer using Josephson junctions by IBM in the 1970¡¯s, the notion has been carried forward that superconducting electronics is a self-contained technology capable of providing all of the features needed to implement a complete general-purse computation system. Yet, despite the demand pull of fast but exceptionally low power operation and a substantial international investment, demonstration of this capability remains projected. In hindsight, this is not a surprise.

In this paper, we will make three points. The first point is cryogenically-operated CMOS can save power when refrigeration costs are included, as lower temperature enables bias voltage reduction which induces the main component of power dissipation to decrease quadratically, and when the Carnot refrigeration factor is included, room-temperature plug-power can trend toward linearity with absolute operating temperature. The DARPA Low Temperature Low Threshold program funding Intel and 17³Ô¹Ï is an important early step in this direction.
The second point will be a frank elucidation of the limitations of the Josephson junction as an implementation medium for complex digital systems. Without analog gain and input/output isolation, some critical features of modern processing systems can not be implemented. For example, tri-state busses and dense memory are critical components that are unavailable in systems based entirely on Josephson junctions. However, these elements are handled with ease by conventional CMOS.

The main point of this paper is to propose semiconductor/Josephson hybrid circuit development, as we envision a path where the two technologies will complement one another in increasing system performance, while mutually mitigating the shortcomings. The bottom line is that by augmenting standard cryo-CMOS with Josephson-based accelerators, one may obtain improved performance and/or reduce system power requirements for some and hopefully many application areas. The semiconductor circuitry can provide the dense memory, control circuitry, and input/output translation that is lacking from pure Josephson technology. As the bias voltage of CMOS is reduced below 200mV, interfacing between the two technologies becomes easier.

We see the initial hybrid systems having multiple-temperature operating environments. This would include a 4K environment containing Josephson and CMOS circuits, potentially fabricated on the same substrate. A second temperature site, probably at 77K, would contain the bulk of the general-purpose processing and memory.
The goal of this paper is to suggest that researchers investigate how the two technologies can be used in a system to complement one another, as this scenario provides a possible path toward zettaflop computing.

To explore the power/performance characteristics of advanced single flux quantum (SFQ) digital technology we are developing a library of cells based on a virtual process, incorporating experimental new design techniques to improve layout density and flexibility. The exercise is providing insight into the benefits of technology which could be available in coming years if resources permit. We have chosen a model process based on demonstrated technology, specifically the Lincoln Laboratory SFQ5ee process, but with a single junction layer consisting of self-shunted 600 ?A/?m²?junctions, which have been fabricated and tested at Lincoln, but have not been explored for manufacturability. We see this process flow as achievable near-term with high probability given low-to-moderate resources.

We chose an energy-efficient SFQ, dc powered approach that we term ¡°YSFQ¡±. The family has several unique experimental features. One feature is the complete lack of geometrical inductors. Instead of inductors, we use lateral Josephson junction arrays, which has the advantages of tracking of effective I_cL product with global I_c?variation for increased circuit yield, reduced sensitivity to magnetic fields for lower crosstalk and lower sensitivity to power currents and trapped flux, and reduced circuit area and greater flexibility of feature placement in layout. We also use a voltage biasing technique similar to ERSFQ, that requires no more than one junction per bias point, and provides a bias current that again tracks the circuit junction critical current, cancelling global variation. The advantage gained from the tracking of circuit variables enables tight control which allows additional features such as wired-OR inputs for cost-free OR logic, and a relatively high interconnect passive transmission line (PTL) impedance of 16 ohms, allowing improved wiring density. The high critical current density junctions provide high speed operation, and self shunting reduces layout area by mostly eliminating damping resistors.

The library contains simple to rather complex gate and latch structures, including Complementary Asynchronous universal and exclusive-OR gates. These are new logic gates that implement a fully asynchronous logic using dual-rail signaling. The modular latches provide capability of up to two independent nondestructive sense amplifiers, each with true and complement outputs.

The objective of this paper is to suggest future avenues for the design of SFQ digital logic, and to stimulate continued advancement in Josephson junction fabrication technology, promising improved density and yield. Advances in circuit design and processing are necessary to further evolve superconducting electronics toward application in future digital systems.