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Category

Feature

Specification Version

CXL 1.1, CXL 2.0, CXL 3.0, CXL IDE, CXL CXS.b, CXL LPIF 1.0, PCIe Base- 5.0/6.0, PIPE- 5.2/6.1

DUT Configuration

HOST, Device

Protocol Support

CXL.io, CXL.cache, CXL.mem, PCIe Only

Interface

Serial PIPE, SERDES, CXL over CXS ULL, CXL Over CXS LLL

Device Type

Type 1 ¨C CXL.io + CXL.cache?

Type 2 ¨C CXL.io + CXL.mem + CXL.cache

Type 3 ¨C CXL.io + CXL.mem

Topology

PCIe TLMs at TL/DL, CXL.io/mem/cache TLM, CXL Flit TLM - CXL Req/ Data/Resp TLM, Logical PHY Interface (LPIF) v 1.1, PCIe LPC, PIPE SerDes Architecture, Serial

Link Speeds

64 GT/s, 32 GT/s and degraded mode of 16 GT/s and 8 GT/s

Link Width

Native Width (x16, x8, and x4) and degraded width (x2, x1)

Security

IDE, DOE

Flit Support

256B standard, 256B Lopt, 68B, and all other flit types supported for each layer

IO/Cache/Mem

All types of IO, Cache and Mem Flows, Back-Invalidation Host, Device Bias mode, Retry flow, Viral and Poison, QoS telemetry

ARB/MUX

All Power Saving states, Weighted Round Robin, Arbitration Bypass mode

Registers

Configuration Space Registers, Memory Mapped Registers

Flex Bus

Alternate Protocol Negotiation, Framing Error Handling, Synch Header Bypass

Initialization and Enumeration

CXL 1.1, 2.0 and 3.0 enumeration, Link Layer Initialization, Bypass Enumeration

Analysis

Protocol Analyzer, Scoreboard, Protocol Checks at each level, Functional Coverage

Simulator

Support all Major Simulators

Methodology

Native SystemVerilog/UVM