17³Ô¹Ï Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial
17³Ô¹Ï Verification IP (VIP) for MIPI SLIMbus (Serial Low-power Inter-chip Media Bus) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI SLIMbus based designs. 17³Ô¹Ï VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Highlights
- Native SystemVerilog/UVM
- Optional source code Test Suites
- Runs natively on all major simulators
- Built-in protocol checks
- Built-in verification plan and coverage
- Extensive error injection
Key Features
- MIPI SLIMbus 2.0 spec
- Supports DATA, Bus and Device control on a single bus
- Operation on Data line 0 to 7
- Bi-directional clock line and data line
- All core messages
- All SLIMbus transport protocols Isochronous, Pushed, Pulled, Asynchronous (Simplex, half-duplex)
- Multiple, concurrent sample rates on a single bus
- Collision Detection for Data channel and Message channel
- Full clock pause
- Active Framer clock recovery mechanism
- Error handling mechanisms
- Dynamic clock frequency change for optimizing bus power consumption
- Established framework for Device creation
- All protocol supported resets
