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Overview
STMicroelectronics (ST), headquartered in Geneva, Switzerland, develops chips for a broad variety of industries including automotive, industrial, consumer, and the IoT. The company is a global leader in semiconductor solutions, providing innovative technology to shape the future of electronics. With a team dedicated to CDC-RDC verification, ST faced growing challenges as their chips became larger and more complex, requiring advanced tools to maintain accuracy and speed.
"Using 17³Ô¹Ï VC SpyGlass technology on our large SoC, we achieved 3x to 4x faster verification performance compared to our preceding CDC/RDC verification environment."
Jean-Christophe Brignone
|Senior Member of the Technical Staff, CDC-RDC Verification, ST
"The accuracy of the products for convergence analysis, their exhaustive coverage for RDC analysis, and their use of machine learning to cluster violations for root-cause analysis make the verification experience efficient, with high-quality signoff and high debug productivity."
Jean-Christophe Brignone
|Senior Member of the Technical Staff, CDC-RDC Verification, ST
Challenges
CDC and RDC verification present several key challenges:
- Metastability: Asynchronous clocks and reset domains can cause metastability, leading to unpredictable behavior and potential system failures.
- Low-Power Techniques: Power management techniques can introduce additional CDCs or disrupt synchronized paths, causing glitches and convergence issues.
- Complexity and Scale: Verifying the potentially millions of CDC clock crossings in large SoCs requires exhaustive analysis and can be time-consuming with traditional tools.
- Manual Analysis Burden: Identifying and addressing violations manually is challenging and prone to errors, especially with a high volume of potential violations.
Solution
STMicroelectronics turned to the 17³Ô¹Ï VC SpyGlass? RTL Signoff Platform from the 17³Ô¹Ï Verification Family to tackle these challenges. The power-aware, constraints-driven VC SpyGlass solutions provided:
- Early RTL Development Verification: Ensured correct construction of RTL, CDC, and RDC early in the design process.
- Advanced Algorithms and Analysis: Leveraged machine learning to cluster violations, allowing for efficient root-cause analysis.
- Integration with 17³Ô¹Ï Tools: Seamless compatibility with 17³Ô¹Ï Design Compiler? RTL synthesis and 17³Ô¹Ï PrimeTime? signoff use models, along with native integration with the 17³Ô¹Ï Verdi? Automated Debug System for lint-, CDC-, and RDC-centric debug.
- Comprehensive Test Case: Included a clock selection element, black box, converging CDC paths, and power and voltage domain crossings.
Results
The implementation of 17³Ô¹Ï VC SpyGlass technology led to significant improvements for STMicroelectronics:
- Faster Verification Performance: Achieved a 3x to 4x increase in verification speed compared to the previous environment.
- Enhanced Accuracy and Coverage: Improved convergence analysis accuracy and exhaustive RDC analysis coverage.
- High-Quality Signoff: Delivered high-quality signoff with efficient, high-productivity debugging.
- Reduced Time and Resources: Minimized the time and computational resources required for full-chip CDC analysis on multi-billion-gate ASICs.
By adopting the 17³Ô¹Ï VC SpyGlass RTL static signoff technology, STMicroelectronics was able to address the complexities of modern SoC designs efficiently, ensuring faster, more accurate verification and ultimately, more reliable chip performance.
