Cloud native EDA tools & pre-optimized hardware platforms
provides tools and IP to safely and efficiently leverage RISC-V¡¯s unprecedented freedom to innovate. As the first-ever multi-sourced commercial-grade ISA, SoC developers need a common RISC-V platform to explore, evaluate, compare, integrate and validate RISC-V subsystems built from a large universe of proprietary and open RISC-V cores. Bluespec integrates deep RISC-V expertise with best-in-class 17³Ô¹Ï EDA tools to provide a powerful out-of-the-box RISC-V development experience that can be easily extended to host any RISC-V core.
This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, 17³Ô¹Ï verification solutions, and RISC-V processor cores from Bluespec.
17³Ô¹Ï VCS? functional verification and Verdi? Debug System solutions are Universal Verification Methodology (UVM) compliant, and seamlessly integrate with Bluespec RISC-V verification flows. The 17³Ô¹Ï' Verification Reference Methodology (VRM) Cookbook for Bluespec RISC-V Processors features Bluespec's RV32I.MCU.AXI4.DM processor, and includes the recommended verification methodology for Bluespecs entire RISC-V processor portfolio.
Optimized and pre-verified full solution stacks for RTOS and Linux RISC-V subsystems are some of the results of Bluespec's collaboration with 17³Ô¹Ï. These stacks provide the hardware and software necessary to evaluate and compare RISC-V cores in bare-metal and virtual memory systems running in the 17³Ô¹Ï VCS? simulator, the Verdi debug platform, and Synplify? synthesis tool. Users can choose system components to evaluate the stacks for specific applications.?
A comprehensive RISC-V software development environment that runs on fast, hardware-emulated RISC-V subsystems in an FPGA-enabled cloud. Any RISC-V subsystem evaluated in the 17³Ô¹Ï environment can be seamlessly accessed in the FPGA cloud for high-speed hardware-accurate validation of software applications