17³Ô¹Ï

Simply Better RTL

The 17³Ô¹Ï RTL Architect product represents the industry¡¯s first physically-aware RTL analysis, exploration, and optimization system with signoff technology integration.

17³Ô¹Ï RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. Built on a unified data model, 17³Ô¹Ï RTL Architect directly leverages 17³Ô¹Ï¡¯ world-class implementation and golden signoff solutions, including 17³Ô¹Ï PrimePower RTL, to deliver results that are accurate early in the design cycle. 17³Ô¹Ï RTL Architect enables designers to significantly reduce RTL development time and to achieve ¡°Simply Better RTL."

Key Benefits

What's New

Predictive RTL Design Closure with 17³Ô¹Ï RTL Architect

Shankar Krishnamoorthy, GM of the EDA Group, discusses the genesis of RTL Architect, 17³Ô¹Ï' new predictive RTL design closure solution..

Developing Your Own RISC-V Processor with Fast Architecture-Driven PPA Optimization

17³Ô¹Ï ASIP Designer and 17³Ô¹Ï RTL 17³Ô¹Ï Architect help designers create highly customized processors faster while meeting the desired PPA targets with confidence.

Your Innovation, Your Community

View the latest RTL Architect customer presentations and papers from SNUG. A  is required.