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Custom Design Family Video Whitepapers
The 17³Ô¹Ï Custom Design Family includes breakthrough technologies in simulation, reliability analysis, analog design closure, layout automation and signoff. Below, 17³Ô¹Ï engineers explain several of the key innovations that make the 17³Ô¹Ï Custom Design Family the most productive on the market.
Design and Verify RFICs ¨C Part 3
In Part 3 of this video series, we provide an overview of custom layout solutions, show post layout verification demonstrating DRC vs. LVS validation, sign-off of EM modeling, and demonstrate final RFIC simulation results within Custom Compiler.
Design and Verify RFICs ¨C Part 2
In Part 2 we will demonstrate EM modeling of inductors using Ansys RaptorX and then demonstrate 17³Ô¹Ï PrimeSim RFIC simulation results analysis using the PrimeWave Design Environment within Custom Compiler.
Design and Verify RFICs ¨C Part 1
In Part I of this 3 part series, we introduce an RF design flow based on 17³Ô¹Ï Custom Design Family which is tightly integrated with Ansys EM solutions. This video describes specification of a LNA amplifier and demonstrates synthesis of the LNA inductor layout.
Demo: SRAM Margin Analysis Workflow
Design and verification of memory chips requires that design and verification tools keep pace with changing requirements and deliver higher capacity, faster runtimes, and advanced reliability analysis within a unified workflow to support designers in their quest for better power, performance, and area while maintaining high design reliability.
Custom Compiler Technology Highlights from 2022.06 Release
Weikai Sun, VP of Engineering at 17³Ô¹Ï, highlights the key technologies in Custom Compiler¡¯s latest release. He shows how 17³Ô¹Ï¡¯ innovative solutions for design closure, layout automation and emerging applications are increasing the productivity of design teams.
Faster Analog Design Closure with Early Parasitic Analysis Flow - Part 2
In part 2 of this series, Denis Goinard, Director of Engineering at 17³Ô¹Ï, discusses how 17³Ô¹Ï provides a unified workflow to accurately measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence.
Faster Analog Design Closure with Early Parasitic Analysis Flow - Part 1
In part 1 of this series, Denis Goinard, Director of Engineering at 17³Ô¹Ï, discusses how 17³Ô¹Ï provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence.
Accelerate Complex RF Designs using Keysight PathWave ADS Platform & Custom Design Platform
Cedric Pujol, Product Manager, Keysight Technologies and Damian Roberts, Sr. Staff AE, 17³Ô¹Ï, demonstrate the unified solution for full flow RFIC design and show how designers are achieving faster layout and design closure with this integrated flow.
Accelerate Custom Layout using Custom Compiler¡¯s User-Defined Device (UDD) ¨C Part 2
In part 2 of this video series, Shabbir Batterywala, 17³Ô¹Ï Scientist, shows how layout designers create complex parameterized custom layout structures in an easy-to-use graphical environment, without any programming.
Accelerate Custom Layout using Custom Compiler¡¯s User-Defined Device (UDD)
In part 1 of this video series, Shabbir Batterywala, 17³Ô¹Ï Scientist, will show how layout designers can create parameterized custom layout structures in an easy-to-use graphical environment, without any programming.
Signoff Quality Early Electrical Analysis Using 17³Ô¹Ï Custom Design Platform
In this 7th video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout.
Effective Design/Layout Collaboration using 17³Ô¹Ï Custom Design Platform
In this 6th video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, discusses methodology innovation in early electrical analysis to reduce iterations, and bringing signoff tools into the design process to speed up analog design closure.
Monte Carlo Analysis using 17³Ô¹Ï Custom Design Platform
In this 5th video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations.
Device Aging Analysis using 17³Ô¹Ï Custom Design Platform
In this 4th video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, explains how device aging effects are more prominent because of stringent operating conditions, and how 17³Ô¹Ï robust aging analysis helps in design for reliability.
Circuit Electrical Rule Checking using 17³Ô¹Ï Custom Design Platform
In this 3rd video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, introduces circuit checks and explains how designers avoid wasted simulation time by finding design and performance problems automatically in advance.
Analog Fault Simulation using 17³Ô¹Ï Custom Design Platform
In this 2nd video of the series, Kai Wang, Director of Engineering at 17³Ô¹Ï, introduces analog fault simulation and explains how 17³Ô¹Ï TestMAX? CustomFault? enables full-chip functional safety and test coverage analysis.
Designing for Reliability using 17³Ô¹Ï Custom Design Platform - Overview
In part I of this video series, Kai Wang, Director of Engineering at 17³Ô¹Ï, will highlight key technologies in 17³Ô¹Ï Custom Design Platform to address reliability challenges across the analog design cycle.
Custom Compiler¡¯s Visually-Assisted Layout Automation in Action
Soni Kapoor, Sr. Technical Marketing Manager in 17³Ô¹Ï¡¯ Custom Design Group, discusses Custom Compiler? Visually-Assisted Layout Automation technology in action as we finish an analog block in one hour that took three days to complete the old-fashioned way.
Quick Start Kits: Process-Optimized 17³Ô¹Ï for Advanced-node Designs
Neel Gopalan, Principal Applications Engineer in 17³Ô¹Ï' Custom Design Group, discusses how Custom Compiler¡¯s Quick Start Kits (QSKs) help designers accelerate layout and reduce design iterations.
Faster Custom Design Closure: Early Layout Feedback for Simulations
Michael Lynch, R&D Director for SerDes IP in 17³Ô¹Ï' 17³Ô¹Ï Group, discusses how using Custom Compiler? Partial Layout Extraction flow significantly reduces design iterations via early electrical analysis.
Visually-Assisted Automation: Graphical Guidance and Real-time Visual Feedback
Custom Compiler? solution speeds layout creation with user-guided routing and reusable templates.
Early Electrical Analysis: Partial Layout Extraction
Custom Compiler? design and layout solution reduces design closure time with signoff-quality early electrical analysis.