17³Ô¹Ï Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial
17³Ô¹Ï Webinar | Available On-Demand
Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. 17³Ô¹Ï VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like 17³Ô¹Ï TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll also highlight the benefits of VC Z01X robust support of the SystemVerilog language. Finally, a practical flow discussion will equip viewers with best practices to get started.
Speakers
Robert Ruiz
Product Management, Sr Director
17³Ô¹Ï
Robert Ruiz is a product management director responsible for strategy and business growth of several verification products at 17³Ô¹Ï. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including 17³Ô¹Ï, Novas Software, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs). Robert has a BSEE degree from Stanford University.
Kirankumar Karanam
Applications Engineer, Manager
17³Ô¹Ï
Kirankumar Karanam is Staff Application Engineer at 17³Ô¹Ï. He currently oversees various customer deployments of 17³Ô¹Ï FuSa verification solutions worldwide. He also works with 17³Ô¹Ï functional verification offerings such as VCS, Verdi, and more. He holds M.S in Software Systems from BITS, Pilani.