17³Ô¹Ï Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial
Watch On-Demand
This year's event brought together 17³Ô¹Ï¡¯ Digital Design Technical Symposium and Verification Day into a single event - 17³Ô¹Ï Silicon Realization TechSummit. Participants from Arm, Broadcom, Datapelago, Deca Technologies, Intel, Microsoft, NVIDIA, NXP, Samsung, SiFive, Stanford University, 17³Ô¹Ï and Ventana Micro shared their insights on three of the hottest industry topics right now; The Move to Multi-Die, Energy Efficient Design and Reliability, Resiliency, Security.
The Move to Multi-Die - Panel
An Industry Perspective on the Coming of Age of Multi-die Design
Panelists:
Jayanthi Pallinti - Broadcom, Craig Bishop - Deca Technologies,
Vivek Rajan - Intel, Sooyong Kim - Samsung,
David Kruckemyer - Ventana Micro
Panel Moderator: Rob Aitken - 17³Ô¹Ï
The Move to Multi-Die - 17³Ô¹Ï Presentation
New Dimensions, New Opportunities: Sparking a New Age of Innovation with Multi-Die Design
Multi-die architectures are emerging as a catalyst, sparking continued innovation and opening up new opportunities in broad market applications, including AI, high-performance computing, and mobile. This presentation will discuss the ¡°coming of age¡± of multi-die design and highlight 17³Ô¹Ï¡¯ software-to-silicon system-level solution that is enabling the next wave of transformative products.
Shekhar Kapoor, Sr. Director, Product Marketing, 17³Ô¹Ï
Energy Efficient Design - Panel
1000X Improvement in Energy Efficiency: What¡¯s a chip got to do with it?
Panelists:
Anand Iyer - Datapelago, Atul Walimbe - Intel,??
Bijal Shah -?NVIDIA,?Rohit Kumar -?SiFive,?
Vishal Khandelwal -?17³Ô¹Ï
?
Panel Moderator:?Rob Aitken?-?17³Ô¹Ï
Energy Efficient Design - 17³Ô¹Ï Presentation
A Vision for Software-Driven Energy Efficient Design
17³Ô¹Ï presents industry trends for energy efficient design, along with its vision and solutions for a ¡®shift-left¡¯ methodology. Topics include architectural tradeoffs, power profiling with real software workloads, RTL design for low power, RTL power regressions, power-driven implementation, and power signoff.
Solaiman Rahim, Group Director, R&D, 17³Ô¹Ï
Reliability, Resiliency, Security - Panel
What is the Cure for All Our Reliability, Resiliency, and Security Woes?
Panelists:
Ghani Kanawati -?Arm,?Serge Leef -?Microsoft,??
Vatsa Prahallada -?NXP,??Subhasish Mitra -?Stanford University
?
Panel Moderator:?Adam Cron -?17³Ô¹Ï
Reliability, Resiliency, Security - 17³Ô¹Ï Presentation
Reliable and Secure Silicon Throughout the Lifecycle
The future of silicon health management is hardware analytics and test. In this session you will learn how 17³Ô¹Ï verification, signoff and silicon lifecycle management (SLM) solutions are enabling secure, reliable, and resilient silicon.
Adam Cron, Distinguished Architect, 17³Ô¹Ï