Complete UALink IP Solution
The 17³Ô¹Ï UALink IP solution, consisting of UALink Controller, PHY, and verification IP, is designed to meet the performance requirements for AI Accelerator to AI Accelerator connections in the scale-up of AI clusters, compliant to the upcoming UALink Consortium specification. The best-in-class IP solution provides a standards-based option for AI hardware required to scale-up high density AI Accelerator to AI Accelerator connections, supporting rates up to 200Gbps per lane. 17³Ô¹Ï¡¯ complete UALink IP delivers a low-risk, standards solution optimized for power, performance, area and latency. Leveraging 17³Ô¹Ï¡¯ extensive PCIe and Ethernet expertise and a proven track record in high-speed networking, AI and HPC SoC designs, designers can accelerate time-to-market and develop best in class AI hardware infrastructure, enabling a path to first pass silicon success.
? Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
? Complete UALink IP solution with Controller, PHY and VIP, fully integrated for AI accelerators (XPUs), GPUs, and switches
? Enables maximum throughput with up to 200Gbps per lane
? Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
? Supports high density / high radix networking infrastructure for AI workloads
? Enables full hardware security needs for UALink specifications