Specialty IO and PHY

17�Թ� Specialty IO library and PHY provide designers with the input/output operation, functionality and reliability required for SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. Available in many foundries and process technologies from 3nm to 22nm, the specialty IO library supports multiple voltages and a complete set of support cells (supply, corner spacers, diode breakers, terminators). 17�Թ� Specialty IOs meet critical power, performance, area (PPA), and reliability requirements for standards including LVDS, sLVDS, eMMC, I2C, I3C, and xSPI.

17�Թ� Low Voltage Differential Signaling (LVDS) IO

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17�Թ� Low Voltage Differential Signaling (LVDS) IO library is a high-frequency interface that uses differential signals for data transmission. A few typical LVDS IO applications are in display monitors, printers, high-speed clock transfers, and high-speed SERDES. 17�Թ� LVDS IO library is used to build an LVDS-based interface for high-speed interconnect applications. This library is designed to optimize IO performance with a core voltage of 0.75 V and supports an IO supply voltage of 1.2V/1.5 V. The library contains a transmitter, a receiver, and a bandgap reference circuit that is used to supply the current reference for the transmitter/receiver. The LVDS IO library is compatible with the IEEE standard 1596.3-1996 and TIA/EIA - 644 -A. Key Features are:

Maximum operating speed: up to 3.4GBPS
Compatibility with TIA/EIA - 644-A for greater interoperability
Loop back option supported for both Pre/Post driver in LVDS TX
HBM 2KV, CDM 500V (up to 7A)
Silicon validated IP
Automotive G1/G2 supported, ASIL-B certified
Designed to support multiple metal stack options
Support for flip-chip & wirebond packaging

17�Թ� Inter-Integrated Circuit (I2C) IO

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17�Թ� Inter-Integrated Circuit (I2C) IO library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters and microcontrollers on the same bus. It is designed for higher IO voltage supply with support for low core voltage and includes fail-safe and fail-tolerance options. The following operating modes are supported:

Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast-Plus Mode: 1 MHz
High-Speed Mode: 3.4 MHz

Key features are:

Input Schmitt trigger
Compliance with I2C-bus specification and User Manual�CApril4, 2014, with I2C operating modes
Filter of 50 ns for Spike rejection
Automotive G1/G2 supported, ASIL-B certified
Silicon validated IP
ESD: 2KV HBM, 500V(up to 7A) CDM, Latch-up: +/-100mA @ 150?C
Designed to support multiple metal stack options
Support for flip-chip & wirebond packaging

17�Թ� I3C IO

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17�Թ� I3C IO library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can be controlled by one I3C primary device at a time. It offers backward compatibility with I2C legacy devices, is designed for high IO voltage domains and supports low-core voltage domains. The I3C incorporates the Schmitt-Trigger function, supports I2C Legacy Fast Mode and FM+ Mode, and includes HBM and CDM ESD protection. We provide an interoperable validated I3C IO solution with our in-house 17�Թ� I3C controllers. The library supports independent power sequencing with the support of a power management cell from our base libraries. The 17�Թ� I3C IO specifications align with the latest JEDEC standards and support:

Push-pull (12.5 MHz) and Open drain I3C modes (1MHz)
I2C Legacy Fast Mode (400KHz) and Fm+(1MHz) Mode

Key Features are:

Support Schmitt trigger
50 ns filter for spike rejection
Automotive G1/G2 supported, ASIL-B certified
Silicon-validated IP
Interoperable validated I3C IO solution with our in-house 17�Թ� I3C Controllers
HBM 2KV, CDM 500V(up to 7A), Latch-up: +/-100mA @ 125?C
Designed to support multiple metal stack options
Support for flip-chip & wire bond packaging
Silicon-proven solution

17�Թ� SD/eMMC PHY, SDIO, eMMC IO

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17�Թ� SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. 17�Թ� SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations. It includes an optional digi logic circuitry which is required for high-speed operations. It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards. The fey features are:

Completely hardened PHY solution along with programmable delay chains & IOs
Fully selectable output impedance
Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
Automotive G1/G2 supported, ASIL-B certified
Interoperability checks done with 17�Թ� Controllers
HBM 2KV, CDM 500V(up to 7A), Latch-up: +/-100mA @ 125?C
Silicon validated IP
Designed to support multiple metal stack options
Support for flip-chip & wirebond packaging

17�Թ� Programmable Crystal Oscillator

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17�Թ� offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter and to support wide operation. In addition, the bypass mode is supported with a maximum frequency of 50 MHz. Key features are:

Bypass mode supported with a maximum frequency of 50 MHz
Power down mode supported
Support for Independent supply sequencing of IO and core supply
Flip-chip packaging support
Automotive G1/G2 supported, ASIL-B certified
HBM 2KV, CDM 500V(up to 7A), Latch-up: +/-100mA @ 125?C
Silicon validated IP
Designed to support multiple metal stack options

17�Թ� xSPI PHY, xSPI IO

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17�Թ� xSPI PHY is a fully integrated hardened macro with high-speed IOs and a delay-locked loop (DLL). The PHY provides impedance matching to ensure signal integrity and higher performance with eight IOs, eases integration challenges, and provides area-optimized solutions and compatibility with various standards.

Fully Hardened xSPI PHY Solution

Compliant with JESD251, JESD216C
Supports a nominal 200MHz data rate, provided by the reference clock (and integer divisions)
ESD : 2KV HBM, 6A(250v) CDM, Latch up: +/-100mA @ 125?C
Configurable Bus width mode: 1-bit, 8-bit

Integrated (Readymade) and area-optimized

Fully optimized, compliant and interoperable solution with Delay lines and Area optimized IO��s
Includes a DLL to facilitate clock and data strobe phase delays

Consistent delay line granularity/resolution across PVT