USB2.0 On-The-Go Controller IP

The 17�Թ� Hi-Speed USB 2.0 On-The-Go (HS OTG) Controller provides designers with high-quality USB IP for the most demanding USB 2.0 peripherals. The controller performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 Hi-Speed peripheral, or Hi-Speed USB 2.0 Host. Based on 17�Թ�' success in building and deploying Hi-Speed USB 2.0 Host, Device and PHY designs, the 17�Թ� USB 2.0 HS OTG Controller incorporates 17�Թ� expertise in Reuse Methodology, Constrained Random Verification, and USB PHY interoperability to deliver flexible, quality IP in Verilog source. The controller is optimized for area- and power-sensitive markets such as Internet of Things (IoT).

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17�Թ� USB 2.0 Controller IP

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Hardware state machines maximize performance and minimize CPU interrupts
Flexible parameters enable easy integration into low and high-latency systems
Integrated DMA offloads CPU and system bus
Configurable data buffering options fine-tune performance/area trade-offs
Buffer and descriptor pre-fetching maximizes host throughput
Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
Simulated for millions of hours through extensive Constrained Random Verification
AMBA High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
UTMI+ Level 3 enables rapid integration with compatible PHYs
Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) operation

USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)

STARs

Description:	USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
Name:	dwc_usb_2_0_hs_otg_subsystem-ahb
Version:	5.00b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Integrating HS OTG Controller and USB 2.0 femtoPHY Application Note ( PDF \| HTML ) Databooks 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Databook (5.00b) ( PDF \| HTML ) 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Databook with Change Bars (5.00a) ( PDF ) Datasheet 17�Թ� USB 2.0 Controller IP ( PDF ) Installation Guide 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Installation Guide (5.00b) ( PDF \| HTML ) Programming Guides 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide (5.00b) ( PDF \| HTML ) 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide with Change Bars (5.00a) ( PDF ) Release Notes 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) Release Notes (5.00b) ( PDF ) Success Stories ChipWrights achieves first-pass silicon success and meets aggressive schedule with high-quality 17�Թ� USB and Ethnernet IP ( PDF ) Combination of Tools, IP and Services Help Teradici Achieve First Silicon Success ( PDF ) High Quality IP Saves Open-Silicon Three Months on Schedule ( PDF ) 17�Թ� Hi-Speed USB 2.0 OTG PHY and Controller IP Shortens austriamicrosystems Project by up to Six Months ( PDF ) User Guides 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) User Guide (5.00b) ( PDF \| HTML ) 17�Թ� Controller IP USB 2.0 Hi-Speed On-The-Go (OTG) User Guide with Change Bars (5.00a) ( PDF ) White Paper Shrinking SoC Design Cycles Using 17�Թ� Intellectual Property ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_otg
Product Code:	3884-0