PCI Express 3.0 PHY IP

The multi-channel 17�Թ� PHY IP for PCI Express 3.1 includes 17�Թϡ� high-speed, high-performance transceiver to meet today��s applications�� demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today��s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using the leading-edge design, analysis, simulation, and measurement techniques, 17�Թ� delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

17�Թ� offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, 17�Թ�' solution is in volume production and has been successfully implemented in a wide range of applications.

17�Թ� IP for PCI Express Complete Solution Datasheet
17�Թ� PHY IP for PCI Express 3.1

Highlights

Products

Downloads and Documentation

Compliant with the PCI Express (PCIe?) 3.1, 2.1, 1.1 and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
L1 substate and SRIS support
Power gating and power island
Embedded Bit Error Rate (BER) tester and internal eye monitor
Build-in Self Test vectors, PRBS generation and checker
IEEE 1149. 6 AC JTAG Boundry Scan
Supports -40C to 125C junctions
Supports optional wirebond and flip-chip packaging

10G PHY for PCIe 3.0, TSMC 16FFC x2, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2	STARs	Subscribe
10G PHY for PCIe 3.0, GF 22FFDSOI X1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, SS 8LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC N5 X2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC5FF X4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 6FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 6FF x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 6FF x4, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation	STARs	Subscribe
8G2 PHY for PCIe 3.0, TSMC 22ULP x2, North/South (vertical) poly orientation	STARs	Subscribe
8G2 PHY for PCIe 3.0, TSMC 22ULP x4, North/South (vertical) poly orientation	STARs	Subscribe
8G2 PHY for PCIe 3.0, UMC 22ULP x4, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPCP x1, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPCP x2, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPCP x4, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPCP x8, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPC x1, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPC x2, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientation	STARs	Subscribe
8G PHY for PCIe 3.0, TSMC 28HPC x8, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, GF 12LP, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N3E, North/South (vertical) poly orientation	STARs	Subscribe
Differential Buffer, TSMC N5, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N6, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, GF 22FFDSOI X2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, GF 22FFDSOI x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientation	STARs	Subscribe
PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientation	STARs	Subscribe
PCIe 3.0 PHY, SS SF5A, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, TSMC 12FFCP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, TSMC 28HPM x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, TSMC N4P x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, UMC 28HPC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 3.0 PHY, UMC 28HPC x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for Differential Buffer, GF 12LP, North/South (vertical) poly orientation
Name:	dwc_diffbuf_gf12lp_ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for GF 12 LP (PHY Version: 1.00a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for GF 12 LP (PHY Version: 1.00a) ( TEXT )
Download:	DiffBuf_NS_GF_12LP
Product Code:	E099-0

Description:	10G PHY for Differential Buffer, TSMC N3E, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc3eff_ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Core Differential Buffer for TSMC3eFF Databook (PHY Version:3.02a) ( PDF \| HTML ) Release Notes DesignWare Core Differential Buffer for TSMC3eFF Release Notes (PHY Version: 3.02a) ( TEXT )
Download:	dwc_diffbuf_tsmc3eff_ns
Product Code:	G450-0

Description:	10G PHY for Differential Buffer, TSMC N6, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc6ff_ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 6FF Databook (PHY Version:3.00a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 6FF (PHY Version: 3.00a) ( TEXT )
Download:	dwc_diffbuf_tsmc6ff_ns
Product Code:	H149-0

Description:	10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc7ff_ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for TSMC 7FF (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 7FF (PHY Version: 2.09a) ( TEXT )
Download:	dwc_diffbuf_tsmc7ff_ns
Product Code:	C522-0

Description:	10G PHY for PCIe 3.0, GF 22FFDSOI X1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_gf22fdsoiext_x1ns
Version:	2.04c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.80a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores PCIe 3.1 PHY (PCS Version: 3.2.6) ( PDF \| HTML ) DesignWare Cores Consumer 10G PCIe3 PHY for GF 22FDSOI-EXT (PHY Version: 2.04c) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe3 x1 NS for GF 22FDSOIEXT 1.8V (PHY Version: 2.04c) ( TEXT )
Download:	dwc_c10pcie3phy_gf22fdsoiext_x1ns
Product Code:	E187-0

Description:	10G PHY for PCIe 3.0, SS 8LPP x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_ss8lpp_x2ns
Version:	1.01b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for SS8LPP ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.1 PCS for the DesignWare Cores Consumer PCIe 3.1 PHY for SS 8 LPE (PHY Version: 1.01a) ( PDF \| HTML ) DesignWare Cores Consumer 10G PCIe 3.1 PHY for SS 8 LPE Databook (PHY Version: 1.01b_d2) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY x1 NS for SS 8 LPE Release Notes (PHY Version: 1.01a) ( TEXT )
Download:	dwc_c10pcie3phy_ss8lpp_x2ns
Product Code:	F495-0

Description:	10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc10ffx1ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) DesignWare Cores Consumer 10 PCIe 3.0 PHY for TSMC 10 FF ( PDF ) Datasheets 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_10FF_x1
Product Code:	B942-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx1ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 10G PCIe 3.1 PHY x1 for TSMC 12 FFC Databook (PHY Version: 1.07a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52b) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes Consumer 10G PCIe 3.1 PHY x1 for TSMC 12 FFC Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx1ns
Product Code:	C478-0, F900-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx2ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY x2 for TSMC12FFC Databook (PHY Version: 1.07a)) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52c) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes PCIe 3.0 PHY x2 NS for TSMC 12FFC 1.8V Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx2ns
Product Code:	C479-0

Description:	10G PHY for PCIe 3.0, TSMC 12FFC x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc12ffcx4ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC12FFC x4 (PHY Version: 1.07a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52a) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes Consumer PCIe 3.0 PHY for TSMC12FFC x4 NS 1.8V (PHY Version: 1.07a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc12ffcx4ns
Product Code:	C480-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x1ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52b) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for TSMC16FFC x1 (PHY Version: 1.10a_d1) ( PDF \| HTML ) Datasheets 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x1 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x1ns
Product Code:	B988-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x16ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench for TSMC16 ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 for TSMC16 PHY ( PDF ) Datasheets 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
Download:	PCIe-30-PHY_C10_TSMC_16FFC_x16
Product Code:	C420-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x2, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name:	dwc_ap_c10pcie3phy_tsmc16ffc_x2ns
Version:	1.06a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 3.1 PHY for TSMC16 FFC ATE Test Bench Application Note (PHY Version: 1.05a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer PCIe 3.0 PCS for the DesignWare Cores Consumer PCIe 3.0 PHY (PHY Version: 1.06a) ( PDF \| HTML ) DesignWare Cores 10G AP PCIe 3.0 PHY for TSMC16FFC Databook (PHY Version: 1.06a_d1) ( PDF \| HTML ) Datasheet 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G AP PCIe 3.0 PHY for TSMC16FFC Release Notes (PHY Version: 1.06a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF ) White Paper IP for Centralized ADAS Domain Controllers ( PDF )
Download:	dwc_ap_c10pcie3phy_tsmc16ffc_x2ns
Product Code:	C085-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x2ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52c) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for TSMC16FFC x2 Databook (PHY Version: 1.10a_d1) ( PDF \| HTML ) Datasheets 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores USB 3.1 SS+ PHY for TSMC16FFC x2 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x2ns
Product Code:	C047-0

Description:	10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc16ffc_x4ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.52a) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for TSMC16FFC x4 Databook (PHY Version: 1.10a_d1) ( PDF \| HTML ) Datasheets 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 10G PHY IP Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC16FFC x4 Release Notes (PHY Version: 1.10a) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
Download:	dwc_c10pcie3phy_tsmc16ffc_x4ns
Product Code:	B943-0

Description:	10G PHY for PCIe 3.0, TSMC 6FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc6ff_x1ns
Version:	4.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3 PHY ATE Test Bench (Doc Version: 1.90b) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) Databooks 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for TSMC6FFx1 Databook (PHY Version: 4.04a) ( PDF \| HTML ) 17�Թ� PHY IP PCIe 3.1 PCS for PCIe 3.1 PHY PHY/PCS Wrapper Databook (PCS Version: 3.54j) ( PDF \| HTML ) Reference Manual 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for TSMC6FF Reference Manual (PHY Version: 4.04a) ( PDF \| HTML ) Release Notes 17�Թ� PHY IP Consumer 10 PCIe 3.1 PHY x1 for TSMC6FF 1.8V Release Notes (PHY Version: 4.04a) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc6ff_x1ns
Product Code:	F849-0

Description:	10G PHY for PCIe 3.0, TSMC 6FF x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc6ff_x2ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.90a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) 17�Թ� PHY IP PCIe 3 PHY ATE Test Bench (Doc Version: 2.10a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC6FF x2 Databook (PHY Version: 4.03b_d2) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores C10 PCIe 3.1 PHY (PCS Version: 3.54a) ( PDF \| HTML ) Release Notes DWC Consumer 10 PCIe 3.1 PHY x2 for TSMC6FF 1.8V Release Notes (PHY Version: 4.03b) ( TEXT )
Download:	dwc_c10pcie3phy_tsmc6ff_x2ns
Product Code:	F850-0

Description:	10G PHY for PCIe 3.0, TSMC 6FF x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc6ff_x4ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Code:	F851-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x1ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench (Doc Version: 1.90a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) 17�Թ� PHY IP PCIe 3 PHY ATE Test Bench (Doc Version: 2.10a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10 PCIe 3.1 PHY for TSMC7FF (PHY Version: 4.03b) ( PDF \| HTML ) 17�Թ� PHY IP PCIe 3.1 PCS for PCIe 3.1 PHY PHY/PCS Wrapper Databook (PCS Version: 3.54j) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Release Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY x1 NS for TSMC 7FF 1.8V Release Notes (PHY: Version 4.03b) ( TEXT ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With 17�Թ� IP Portfolio ( PDF ) ��˼�Ƽ��о�Ƽ� ��о�Ƽ��˼�Ƽ��17�Թ� IPϵ��ʵ��SSD�� ( PDF )
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Product Code:	C476-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x2ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Download:	dwc_c10pcie3phy_tsmc7ff_x2ns
Product Code:	C477-0

Description:	10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc7ff_x4ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Code:	C605-0

Description:	10G PHY for PCIe 3.0, TSMC N5 X2, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc5ff_x2ns
Version:	4.01c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Code:	E458-0

Description:	10G PHY for PCIe 3.0, TSMC5FF X4, North/South (vertical) poly orientation
Name:	dwc_c10pcie3phy_tsmc5ff_x4ns
Version:	4.01c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Download:	dwc_c10pcie3phy_tsmc5ff_x4ns
Product Code:	E459-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPC x1, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpc_x1ns
Version:	1.04d
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.12) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare? Cores Consumer 8G PCIe 3.0 One-Lane PHY for TSMC 28 HPC Databook (PHY Version: 1.04d) ( PDF \| HTML ) DesignWare? Cores Consumer 8G PCIe 3.0 One-Lane PHY for TSMC 28 HPC Databook with Change Bars (PHY Version: 1.04d) ( PDF ) Datasheets 17�Թ� Consumer 8G PHY Datasheet ( PDF ) 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 8G PHY Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores Consumer 8G One-Lane PHY for TSMC 28 HPC Release Notes (PHY Version: 1.04d) ( TEXT )
Download:	PCIe-30-PHY_TSMC_28HPC_x1
Product Code:	A729-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPC x2, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpc_x2ns
Version:	1.04e
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY ( PDF ) Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare? Cores Consumer 8G PHY for TSMC 28 HPC Databook (PHY Version: 1.04e) ( PDF \| HTML ) DesignWare? Cores Consumer 8G Two-Lane PHY for TSMC 28 HPC Databook with Change Bars (PHY Version: 1.04e) ( PDF ) Datasheets 17�Թ� Consumer 8G PHY Datasheet ( PDF ) 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 8G PHY Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores Consumer 8G PHY for TSMC 28 HPC (Two Lanes) Release Notes ( TEXT )
Download:	PCIe-30-PHY_TSMC_28HPC_x2
Product Code:	A730-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpc_x4ns
Version:	1.04e
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare? Cores Consumer 8G PHY for TSMC 28 HPC Databook (PHY Version: 1.04e) ( PDF \| HTML ) DesignWare? Cores Consumer 8G Two-Lane PHY for TSMC 28 HPC Databook with Change Bars (PHY Version: 1.04e) ( PDF ) Datasheets 17�Թ� Consumer 8G PHY Datasheet ( PDF ) 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 8G PHY Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores Multi-Protocol 8G PHY for TSMC 28 HPC (Four Lanes) Release Notes ( TEXT ) Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with 17�Թ� DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF ) AMD��14��׹��գ��Ƴ��DesignWare DDR4��USB 3.0��PCIe 3.1��Ethernet and Foundation IP��ҵ��ȵ�Ryzen��EPYC�� ( PDF )
Download:	PCIe-30-PHY_TSMC_28HPC_x4
Product Code:	A731-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPC x8, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpc_x8ns
Version:	1.04e
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare? Cores Consumer 8G PHY for TSMC 28 HPC Databook (PHY Version: 1.04e) ( PDF \| HTML ) DesignWare? Cores Consumer 8G Two-Lane PHY for TSMC 28 HPC Databook with Change Bars (PHY Version: 1.04e) ( PDF ) Datasheets 17�Թ� Consumer 8G PHY Datasheet ( PDF ) 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) 17�Թ� Multi-Protocol 8G PHY Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores Multi-Protocol 8G PHY for TSMC 28 HPC (Eight Lanes) Release Notes ( TEXT )
Download:	PCIe-30-PHY_C8_TSMC_28HPC_x8
Product Code:	A808-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPCP x1, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpcp_x1ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.12) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databook Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF )
Download:	PCIe-30-PHY_C8_TSMC_28HPCP_x1
Product Code:	B637-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPCP x2, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpcp_x2ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.12) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databook Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF )
Download:	PCIe-30-PHY_C8_TSMC_28HPCP_x2
Product Code:	B638-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPCP x4, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpcp_x4ns
Version:	1.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.12) ( PDF ) DesignWare? Cores PCIe 3.0 8G PHY ATE Testbench (Doc Version: 1.13) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare Cores PCIe 3.1 Four-Lane PHY for TSMC 28 HPCP Databook (PHY Version: 1.02b) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores PCIe 3.0 Four-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 1.02b) ( TEXT )
Download:	dwc_c8g_pcie3phy_tsmc28hpcp_x4ns
Product Code:	B639-0

Description:	8G PHY for PCIe 3.0, TSMC 28HPCP x8, North/South (vertical) poly orientation
Name:	dwc_c8g_pcie3phy_tsmc28hpcp_x8ns
Version:	1.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Test Bench (Doc Version: 1.12) ( PDF ) DesignWare? Cores PCIe 3.0 8G PHY ATE Testbench (Doc Version: 1.13) ( PDF ) DesignWare? Cores PCIe 3.0 PHY Unified Power Format (UPF) (Doc Version 1.00a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare Cores PCIe 3.1 Four-Lane PHY for TSMC 28 HPCP Databook (PHY Version: 1.02b) ( PDF \| HTML ) Datasheet 17�Թ� IP for PCI Express Complete Solution Datasheet ( PDF ) Installation Guide DesignWare? Cores Multi-Protocol 8G PHY Installation Guide (Doc Version: 1.00a) ( PDF ) Release Notes DesignWare? Cores PCIe 3.0 Eight-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 1.02b) ( TEXT )
Download:	dwc_c8g_pcie3phy_tsmc28hpcp_x8ns
Product Code:	B640-0

Description:	8G2 PHY for PCIe 3.0, TSMC 22ULP x2, North/South (vertical) poly orientation
Name:	dwc_c8g2_pcie3phy_tsmc22ulp_x2ns
Version:	2.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Consumer 8G PHY ATE Testbench (Doc Version: 1.03) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare Cores PCIe 3.1 Two-Lane PHY for TSMC 22 ULP Databook (PHY Version: 2.02a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 8G Two-Lane PHY for TSMC 22 ULP Release Notes (PHY Version: 2.02a) ( TEXT )
Download:	PCIe-30-PHY_C8_TSMC_22ULP_x2
Product Code:	D815-0

Description:	8G2 PHY for PCIe 3.0, TSMC 22ULP x4, North/South (vertical) poly orientation
Name:	dwc_c8g2_pcie3phy_tsmc22ulp_x4ns
Version:	2.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores PCIe 3.1 8G PHY ATE Test Bench (Doc Version: 1.02) ( PDF ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (September 23, 2016) ( PDF ) DesignWare? Cores PCIe 3.1 Four-Lane PHY for TSMC 22 ULP Databook (PHY Version: 2.01a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 8G Four-Lane PHY for TSMC 22 ULP Release Notes (PHY Version: 2.01a) ( TEXT )
Download:	PCIe-30-PHY_C8_TSMC_22ULP_x4
Product Code:	E190-0

Description:	8G2 PHY for PCIe 3.0, UMC 22ULP x4, North/South (vertical) poly orientation
Name:	dwc_c8g2_pcie3phy_umc22ulp_x4ns
Version:	2.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores PCIe 3.1 8G PHY ATE Test Bench (Doc Version: 1.03) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks Consumer 8G PCIe 3.0 PCS for the DesignWare? Cores Consumer 8G PHY (January 11, 2019) ( PDF ) DesignWare? Cores PCIe 3.1 Four-Lane PHY for UMC 22 ULP Databook (PHY Version: 2.00a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 8G Four-Lane PHY for UMC 22 ULP Release Notes (PHY Version: 2.00a) ( TEXT )
Download:	dwc_c8g2_pcie3phy_umc22ulp_x4ns
Product Code:	E981-0

Description:	Differential Buffer, TSMC N5, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc5ff_ns
Version:	3.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 5FF (PHY Version:3.07a_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 5FF (PHY Version: 3.07a) ( TEXT )
Download:	dwc_diffbuf_tsmc5ff_ns
Product Code:	F690-0

Description:	PCIe 3.0 PHY, GF 22FFDSOI X2, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_gf22fdsoiext_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Description:	PCIe 3.0 PHY, GF 22FFDSOI x4, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_gf22fdsoiext_x4ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Description:	PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientation
Name:	dwc_pcie3phy_gf28hpp_x4ew
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Enterprise 10G PCIe 3.0 PHY for GLOBALFOUNDRIES 28 HPP ( PDF ) Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with 17�Թ� DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF ) AMD��14��׹��գ��Ƴ��DesignWare DDR4��USB 3.0��PCIe 3.1��Ethernet and Foundation IP��ҵ��ȵ�Ryzen��EPYC�� ( PDF ) White Paper Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
Download:	PCIe-30-PHY_GF_28HPP_x4EW
Product Code:	9022-0

Description:	PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientation
Name:	dwc_pcie3phy_gf28hpp_x8ew
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Enterprise 10G PCIe 3.0 PHY for GLOBALFOUNDRIES 28 HPP ( PDF ) Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with 17�Թ� DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF ) AMD��14��׹��գ��Ƴ��DesignWare DDR4��USB 3.0��PCIe 3.1��Ethernet and Foundation IP��ҵ��ȵ�Ryzen��EPYC�� ( PDF ) White Paper Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
Download:	PCIe-30-PHY_GF_28HPP_x8EW
Product Code:	9023-0

Description:	PCIe 3.0 PHY, SS SF5A, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_sssf5a_x2ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 1.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations Application Note (Doc Version: 2.00a) ( PDF \| HTML ) 17�Թ� PHY IP PCIe 3 PHY ATE Test Bench (Doc Version: 2.10a) ( PDF \| HTML ) Databooks PCIe 3.1 PCS for the 17�Թ� PHY IP PCIe 3.1 PHY (PCS Version: 3.26d) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for SS5LPE PHY Databook (PHY Version: 2.09a) ( PDF \| HTML ) Reference Manuals 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for SS5LPE PHY Reference Manual (PHY Version: 2.09a) ( PDF \| HTML ) 17�Թ� PHY IP Consumer 10G PCIe 3.1 PHY for SS5LPE PHY Reference Manual with Changes (PHY Version: 2.09a) ( PDF ) Release Notes 17�Թ� PHY IP PCIe3 x2 NS PHY for SS 5LPE 1.8V Release Notes (PHY Version: 2.09a) ( TEXT )
Download:	dwc_pcie3phy_sssf5a_x2ns
Product Code:	I840-0

Description:	PCIe 3.0 PHY, TSMC 12FFCP x2, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_tsmc12ffcpx2ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 PCIe 3.1 PHY ATE Test Bench Application Note (Doc Version: 1.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC12FFC x2 PHY Databook(PHY Version: 1.00a) ( PDF \| HTML ) PCIe 3.1 PCS for the DesignWare Cores Consumer 10G PCIe 3.1 PHY (PCS Version: 3.55a) ( PDF \| HTML ) Reference Manual DesignWare Cores Consumer 10G PCIe 3.1 PHY for TSMC12FFC x2 PHY Reference Manual(PHY Version: 1.00a) ( PDF \| HTML ) Release Notes PCIe 3.1 PHY x2 NS for TSMC 12FFC 1.8V Release Notes (PHY Version: 1.00a) ( TEXT )
Download:	dwc_pcie3phy_tsmc12ffcpx2ns
Product Code:	H727-0

Description:	PCIe 3.0 PHY, TSMC 28HPM x16, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_tsmc28hpm_x16ns
Version:	1.12a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Enterprise 10G PCIe 3.0 PHY ATE Test Bench ( PDF ) Databooks Current Databook with Change Bars ( PDF ) DesignWare? Cores Enterprise 10G PCIe 3.0 PHY for TSMC 28 HPM ( PDF ) Enterprise 10G PCIe 3.0 PCS for the DesignWare? Cores Enterprise 10G PCIe 3.0 PHY ( PDF )
Download:	PCIe-30-PHY_TSMC_28HPM_x16
Product Code:	A278-0

Description:	PCIe 3.0 PHY, TSMC N4P x2, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_tsmc4ffp_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Description:	PCIe 3.0 PHY, UMC 28HPC x1, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_umc28hpc_x1ns
Version:	1.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Enterprise 12G PHY ATE Testbench (Doc Version: 1.12a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP External SRAM Interface and Firmware Loading (Doc Version: 4.00a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare? Cores Multi-Protocol 12G One-Lane PHY for UMC 28 HPC Databook (PHY Version 1.03b) ( PDF ) Enterprise 12G PCIe 3.0 PCS for the DesignWare? Cores Enterprise 12G PHY Databook (June 1, 2015) ( PDF ) Enterprise 12G SATA Rate 6G PCS for the DesignWare? Cores Enterprise 12G PHY (June 1, 2015) ( PDF ) Release Notes DesignWare? Cores Enterprise 12G One-Lane PHY for UMC 28HPC Release Notes (PHY Version: 1.03b) ( TEXT )
Download:	PCIe-30-PHY_E12_UMC_28HPC_x1
Product Code:	C662-0

Description:	PCIe 3.0 PHY, UMC 28HPC x4, North/South (vertical) poly orientation
Name:	dwc_pcie3phy_umc28hpc_x4ns
Version:	1.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Enterprise 12G PHY ATE Test Bench (Doc Version: 1.10) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks DesignWare? Cores Multi-Protocol 12G Four-Lane PHY for UMC 28 HPC Databook (PHY Version: 1.04a) ( PDF ) Enterprise 12G PCIe 3.0 PCS for the DesignWare? Cores Enterprise 12G PHY Databook (June 1, 2015) ( PDF ) Enterprise 12G SATA Rate 6G PCS for the DesignWare? Cores Enterprise 12G PHY (June 1, 2015) ( PDF ) Release Notes DesignWare? Cores Enterprise 12G Four-Lane PHY for UMC 28HPC Release Notes (PHY Version: 1.04a) ( TEXT )
Download:	PCIe-30-PHY_E12_UMC_28HPC_x4
Product Code:	D383-0