PCI Express 2.0 PHY IP

The multi-channel 17�Թ� PHY IP for PCI Express? 2.1 includes 17�Թϡ� high-speed, high-performance transceiver to meet today��s demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today��s PCI Express (PCIe?) designs while being extremely low in power and area.

Using the leading-edge design, analysis, simulation, and measurement techniques, 17�Թ� delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

17�Թ� PHY IP for PCI Express 2.1
17�Թ� IP for PCI Express Complete Solution Datasheet

Highlights

Products

Downloads and Documentation

Compliant with the PCI Express (PCIe?) 2.1 and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
PCIe L1 substate power management
Supports power gating and power island
Embedded bit error rate tester and internal eye monitor
ATE test vectors for complete, at-speed production testing
Pseudo random bit sequencer (PRBS) generation and checker
IEEE 1149.6 AC JTAG Boundry Scan
Beaconing, receiver detection and electrical idle features
Supports -40C to 125C junction temperatures

10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 40LP25, x1 - MP	STARs	Subscribe
PCIe 2.0 PHY, TSMC 40LP, x2	STARs	Subscribe
PCIe 2.0 PHY, TSMC 40LP, x4	STARs	Subscribe
PCIe 2.0 PHY, FUJ 40LP, x1	STARs	Subscribe
PCIe 2.0 PHY, FUJ 40LP, x2	STARs	Subscribe
PCIe 2.0 PHY, FUJ 40LP, x4	STARs	Subscribe
PCIe 2.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 12LP+ x2 North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 12LP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 22FDX x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 28SLP x1, East/West (horizontal) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 28SLP x2, East/West (horizontal) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 28SLP x4, East/West (horizontal) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, GF 40LP, x1	STARs	Subscribe
PCIe 2.0 PHY, GF 40LP, x4	STARs	Subscribe
PCIe 2.0 PHY LP18, TSMC 28HPCP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 LP PHY, TSMC 28HPCP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 40ULP25 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, SMIC 40LL, x1	STARs	Subscribe
PCIe 2.0 PHY, SMIC 40LL, x2	STARs	Subscribe
PCIe 2.0 PHY, SMIC 40LL, x4	STARs	Subscribe
PCIe 2.0 PHY, TSMC 12FFC18 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 12FFC18 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC+ x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC+ x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC+ x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, UMC 40LP, x1	STARs	Subscribe
PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation
Name:	dwc_c10pcie2phy_tsmc7ff_x1ns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G PCIe 2 PHY ATE Test Bench (Doc Version: 1.70a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Consumer 10 PCIe 2.1 PHY for TSMC7FF (PHY Version: 4.03b) ( PDF \| HTML ) PCIe 2.1 PCS for the DesignWare Cores C10 PCIe 2.1 PHY (PCS Version: 3.54a) ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10 PCIe 2 PHY x1 NS for TSMC7FF 1.8V Release Notes (PHY Version: 4.03b) ( TEXT )
Download:	dwc_c10pcie2phy_tsmc7ff_x1ns
Product Code:	C374-0

Description:	10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation
Name:	dwc_c10pcie2phy_tsmc7ff_x2ns
Version:	2.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Designware Cores Consumer 10 PCIe 2 PHY ATE Test Bench ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) 17�Թ� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks Consumer 10G PCIe 2 PHY for TSMC 7 FF ( PDF ) Consumer PCIe 2 PCS for the DesignWare Cores Consumer PCIe 2 PHY ( PDF \| HTML ) Release Notes DesignWare Cores Consumer 10 PCIe 2 PHY for TSMC 7 FF ( TEXT )
Download:	PCIe-20-PHY_TSMC_N7_x2
Product Code:	E183-0

Description:	PCIe 2.0 LP PHY, TSMC 28HPCP x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_lp_tsmc28hpcp_x1ns
Version:	sprd
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	PCIe-20-LP_TSMC_28HPCP_x1
Product Code:	C228-0

Description:	PCIe 2.0 PHY LP18, TSMC 28HPCP x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_lp18_tsmc28hpcp_x1ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare Cores PCIe 2 PHY LP for TSMC 28-nm HPCP 0.9/1.8 V ( PDF )
Download:	PCIe-20-LP18_TSMC_28HPCP_x1
Product Code:	C661-0

Description:	PCIe 2.0 PHY, FUJ 40LP, x1
Name:	dwc_pcie2phy_fuj40lp_x1
Version:	2.00b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm LP 1.1/2.5 V Databook ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm x1 LP 1.1/2.5 V Release Notes (PHY Version 2.00b) ( TEXT )
Download:	PCIe-20-PHY_FUJ_40LP_x1
Product Code:	C174-0

Description:	PCIe 2.0 PHY, FUJ 40LP, x2
Name:	dwc_pcie2phy_fuj40lp_x2
Version:	2.00b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm LP 1.1/2.5 V Databook ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm x2 LP 1.1/2.5 V Release Notes (PHY Version 2.00b) ( TEXT )
Download:	PCIe-20-PHY_FUJ_40LP_x2
Product Code:	C175-0

Description:	PCIe 2.0 PHY, FUJ 40LP, x4
Name:	dwc_pcie2phy_fuj40lp_x4
Version:	2.00b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm LP 1.1/2.5 V Databook ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for Fujitsu 40-nm x4 LP 1.1/2.5 V Release Notes (PHY Version 2.00b) ( TEXT )
Download:	PCIe-20-PHY_FUJ_40LP_x4
Product Code:	C176-0

Description:	PCIe 2.0 PHY, GF 12LP x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_gf12lp_x2ns
Version:	3.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores PCIe 2 PHY for GF 12-nm x2 LP 0.8/1.8 V Databook (PHY Version: 3.04a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe 2 PHY for GF 12-nm x2 LP 0.8/1.8 V (PHY Version: 3.04a) ( TEXT )
Download:	dwc_pcie2phy_gf12lp_x2ns
Product Code:	E098-0

Description:	PCIe 2.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_gf12lpp_x1ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 12-nm x1 LPP 0.8/1.8 V Databook (PHY Version: 3.00a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 12-nm x1 LPP 0.8/1.8 V Release Notes (PHY Version: 3.00a) ( TEXT )
Download:	dwc_pcie2phy_gf12lpp_x1ns
Product Code:	F021-0

Description:	PCIe 2.0 PHY, GF 12LP+ x2 North/South (vertical) poly orientation
Name:	dwc_pcie2phy_gf12lpp_x2ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 12-nm x2 LPP 0.8/1.8 V Databook (PHY Version 3.00a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 12-nm x2 LPP 0.8/1.8 V Release Notes (PHY Version 3.00a) ( TEXT )
Download:	dwc_pcie2phy_gf12lpp_x2ns
Product Code:	F980-0

Description:	PCIe 2.0 PHY, GF 22FDX x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_gf22fdsoi_x2ns
Version:	3.06c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 22-nm x2 FDSOI 0.8/1.8 V Databook (PHY Version 3.06c) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 2 PHY for GLOBALFOUNDRIES 22-nm x2 FDSOI 0.8/1.8 V Release Notes (PHY Version 3.06c) ( TEXT )
Download:	dwc_pcie2phy_gf22fdsoi_x2ns
Product Code:	H075-0

Description:	PCIe 2.0 PHY, GF 28SLP x1, East/West (horizontal) poly orientation
Name:	dwc_pcie2phy_gf28slp_x1ew
Version:	2.5b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for GLOBALFOUNDRIES 28-nm LP 1.0/1.8 V Databook ( PDF )
Download:	PCIe-20-PHY_GF_28SLP_x1EW
Product Code:	9318-0

Description:	PCIe 2.0 PHY, GF 28SLP x2, East/West (horizontal) poly orientation
Name:	dwc_pcie2phy_gf28slp_x2ew
Version:	2.6a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for GLOBALFOUNDRIES 28-nm LP 1.0/1.8 V Databook ( PDF )
Download:	PCIe-20-PHY_GF_28SLP_x2EW
Product Code:	9319-0

Description:	PCIe 2.0 PHY, GF 28SLP x4, East/West (horizontal) poly orientation
Name:	dwc_pcie2phy_gf28slp_x4ew
Version:	2.6a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for GLOBALFOUNDRIES 28-nm LP 1.0/1.8 V Databook ( PDF )
Download:	PCIe-20-PHY_GF_28SLP_x4EW
Product Code:	9320-0

Description:	PCIe 2.0 PHY, GF 40LP, x1
Name:	dwc_pcie2phy_gf40lp_x1
Version:	2.6b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for GLOBALFOUNDRIES 40-nm LP 1.1/2.5 V Databook ( PDF )
Download:	PCIe-20-PHY_GF_40LP_x1
Product Code:	9940-0

Description:	PCIe 2.0 PHY, GF 40LP, x4
Name:	dwc_pcie2phy_gf40lp_x4
Version:	2.4b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for GLOBALFOUNDRIES 40-nm LP 1.1/2.5 V Databook ( PDF )
Download:	PCIe-20-PHY_GF_40LP_x4
Product Code:	A111-0

Description:	PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_smic28hkmg_x1ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for SMIC 28-nm HKMG 0.9/1.8 V Databook ( PDF ) DesignWare? Cores PCIe 2 PHY for SMIC 28-nm HKMG 0.9/1.8 V Databook With Change Bars (PHY Version: 3.00a) ( PDF )
Download:	PCIe-20-PHY_SMIC_28HK_x1
Product Code:	B838-0

Description:	PCIe 2.0 PHY, SMIC 40LL, x1
Name:	dwc_pcie2phy_smic40ll_x1
Version:	2.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for SMIC 40-nm LL 1.1/2.5 V Databook (PHY Version: 2.10a_d1) ( PDF \| HTML )
Download:	PCIe-20-PHY_SMIC_40LL_x1
Product Code:	9504-0

Description:	PCIe 2.0 PHY, SMIC 40LL, x2
Name:	dwc_pcie2phy_smic40ll_x2
Version:	2.07b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for SMIC 40-nm LL 1.1/2.5 V Databook (PHY Version: 2.10a_d1) ( PDF \| HTML )
Download:	PCIe-20-PHY_SMIC_40LL_x2
Product Code:	9505-0

Description:	PCIe 2.0 PHY, SMIC 40LL, x4
Name:	dwc_pcie2phy_smic40ll_x4
Version:	2.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for SMIC 40-nm LL 1.1/2.5 V Databook (PHY Version: 2.10a_d1) ( PDF \| HTML )
Download:	PCIe-20-PHY_SMIC_40LL_x4
Product Code:	9506-0

Description:	PCIe 2.0 PHY, TSMC 12FFC18 x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc12ffc_x1ns
Version:	3.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare? Cores PCIe 2 PHY for TSMC 12-nm FFC 0.8/1.8 V Databook ( PHY Version: 3.10a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 2 PHY for TSMC 12-nm FFC 0.8/1.8 V Release Notes (PHY Version: 3.10a) ( TEXT )
Download:	dwc_pcie2phy_tsmc12ffc_x1ns
Product Code:	C418-0

Description:	PCIe 2.0 PHY, TSMC 12FFC18 x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc12ffc_x2ns
Version:	3.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare Cores PCIe 2 PHY for TSMC 12-nm x2 FFC 0.8/1.8 V Databook (PHY Version: 3.10a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 12-nm x2 FFC 0.8/1.8 V Release Notes (PHY Version: 3.10a) ( TEXT )
Download:	dwc_pcie2phy_tsmc12ffc_x2ns
Product Code:	C630-0

Description:	PCIe 2.0 PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc16ffc_x1ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 16-nm FFC 0.8/1.8 V Databook ( PDF ) DesignWare? Cores PCIe 2 PHY for TSMC 16-nm FFC 0.8/1.8 V Databook With Change Bars (PHY Version: 3.00a) ( PDF )
Download:	PCIe-20-PHY_TSMC_16FFC_x1
Product Code:	B944-0

Description:	PCIe 2.0 PHY, TSMC 16FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc16ffc_x2ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 16-nm FFC 0.8/1.8 V Databook ( PDF ) DesignWare? Cores PCIe 2 PHY for TSMC 16-nm FFC 0.8/1.8 V Databook With Change Bars (PHY Version: 3.00a) ( PDF )
Download:	PCIe-20-PHY_TSMC_16FFC_x2
Product Code:	C083-0

Description:	PCIe 2.0 PHY, TSMC 28HPC x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpc_x1ns
Version:	2.14a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 28-nm x1 HPC 0.9/1.8 V Databook (PHY Version: 2.14a) ( PDF ) DesignWare? Cores PCIe 2 PHY for TSMC 28-nm x1 HPC 0.9/1.8 V Databook With Change Bars (PHY Version: 2.14a) ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 28-nm x1 HPC 0.9/1.8 V Release Notes (PHY Version: 2.14a) ( TEXT )
Download:	PCIe-20-PHY_TSMC_28HPC_x1
Product Code:	A592-0

Description:	PCIe 2.0 PHY, TSMC 28HPC x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpc_x2ns
Version:	2.07i
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for TSMC 28-nm HPC 0.9/1.8 V Databook ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 28-nm HPC 0.9/1.8 V Release Notes (PHY Version: 2.07i) ( TEXT )
Download:	PCIe-20-PHY_TSMC_28HPC_x2
Product Code:	A593-0

Description:	PCIe 2.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpc_x4ns
Version:	2.7c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF )
Download:	PCIe-20-PHY_TSMC_28HPC_x4
Product Code:	A594-0

Description:	PCIe 2.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpc_x8ns
Version:	2.7c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF )
Download:	PCIe-20-PHY_TSMC_28HPC_x8
Product Code:	A807-0

Description:	PCIe 2.0 PHY, TSMC 28HPC+ x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpcp_x1ns
Version:	3.04b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 28-nm x1 HPCP 0.9/1.8 V Databook (PHY Version: 3.04b) ( PDF \| HTML ) DesignWare? Cores PCIe 2 PHY for TSMC 28-nm HPCP 0.9/1.8 V Databook With Change Bars (PHY Version: 3.04b ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 28-nm x1 HPCP 0.9/1.8 V Release Notes (PHY Version: 3.04b) ( TEXT ) DesignWare Cores PCIe 2 PHY for TSMC 28-nm x4 HPCP 0.9/1.8 V Release Notes (PHY Version: 3.04b) ( TEXT )
Download:	PCIe-20-PHY_TSMC_28HPCP_x1
Product Code:	B626-0

Description:	PCIe 2.0 PHY, TSMC 28HPC+ x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpcp_x2ns
Version:	3.04c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for TSMC 28-nm x2 HPCP 0.9/1.8 V Databook (PHY Version: 3.04c) ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 28-nm x2 HPCP 0.9/1.8 V Release Notes (PHY Version 3.04c) ( TEXT )
Download:	PCIe-20-PHY_TSMC_28HPCP_x2
Product Code:	B627-0

Description:	PCIe 2.0 PHY, TSMC 28HPC+ x4, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_tsmc28hpcp_x4ns
Version:	3.00g
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare? Cores PCIe 2 PHY for TSMC 28-nm HPCP 0.9/1.8 V Databook With Change Bars (PHY Version: 3.04b ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 28-nm x4 HPCP 0.9/1.8 V Release Notes (PHY Version: 3.04b) ( TEXT )
Download:	PCIe-20-PHY_TSMC_28HPCP_x4
Product Code:	B628-0

Description:	PCIe 2.0 PHY, TSMC 40LP, x2
Name:	dwc_pcie2phy-tsmc40lp-x2
Version:	2.11c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 40-nm x2 LP 1.1/2.5 V Databook (PHY Version: 2.11c) ( PDF ) DesignWare? Cores PCIe 2 PHY for TSMC 40-nm LP 1.1/2.5 V Databook With Change Bars (PHY Version: 2.11c) ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 40-nm x2 LP 1.1/2.5 V Release Notes (PHY Version: 2.11c) ( TEXT )
Download:	PCIe-20-PHY_TSMC_40LP_x2
Product Code:	9953-0

Description:	PCIe 2.0 PHY, TSMC 40LP, x4
Name:	dwc_pcie2phy-tsmc40lp-x4
Version:	2.11c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 40-nm x4 LP 1.1/2.5 V Databook (PHY Version: 2.11c) ( PDF ) DesignWare? Cores PCIe 2 PHY for TSMC 40-nm LP 1.1/2.5 V x4 Databook With Change Bars (PHY Version: 2.11c) ( PDF ) Release Notes DesignWare Cores PCIe 2 PHY for TSMC 40-nm x4 LP 1.1/2.5 V Release Notes (PHY Version: 2.11c) ( TEXT )
Download:	PCIe-20-PHY_TSMC_40LP25_x4
Product Code:	4777-0

Description:	PCIe 2.0 PHY, TSMC 40LP25, x1 - MP
Name:	dwc_pcie2phy-mp-tsmc40lp-x1
Version:	2.11c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databooks DesignWare Cores PCIe 2 PHY for TSMC 40-nm x1 LP 1.1/2.5 V Databook (PHY Version: 2.11c) ( PDF \| HTML ) DesignWare? Cores PCIe 2 PHY for TSMC 40-nm x1 LP 1.1/2.5 V Databook With Change Bars (PHY Version: 2.11c) ( PDF )
Download:	PCIe-20-PHY_TSMC_40LP25_x1
Product Code:	4775-0

Description:	PCIe 2.0 PHY, TSMC 40ULP25 x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_mpp_tsmc40ulp25_x1
Version:	2.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare? Cores PCIe 2 PHY for TSMC 40-nm ULP x1 1.1/2.5 V Databook (PHY Version: 2.00a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 2 PHY for TSMC 40-nm ULP x1 1.1/2.5 V Release Notes (PHY Version: 2.00a) ( TEXT )
Download:	dwc_pcie2phy_mpp_tsmc40ulp25_x1
Product Code:	F532-0

Description:	PCIe 2.0 PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_umc28hpcp_x1ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare Cores PCIe 2 PHY for UMC 28-nm HPCP 0.9/1.8 V Databook ( PDF )
Download:	PCIe-20-PHY_UMC_28HPCP_x1
Product Code:	C604-0

Description:	PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_umc28hpcp_x2ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie2phy_umc28hpcp_x2ns
Product Code:	E185-0

Description:	PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_umc40lp_x2ns
Version:	2.2a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	PCIe-20-PHY_UMC_40LP_x2
Product Code:	7327-0

Description:	PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation
Name:	dwc_pcie2phy_umc40lp_x4ns
Version:	2.2a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for UMC 40-nm LP 1.1/2.5 V Databook ( PDF )
Download:	PCIe-20-PHY_UMC_40LP_x4
Product Code:	7328-0

Description:	PCIe 2.0 PHY, UMC 40LP, x1
Name:	dwc_pcie2phy_umc40lp_x1
Version:	2.0a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Using the TIAO USB Multi-Purpose Adapter to Access JTAG on 17�Թ� IP ( PDF ) Databook DesignWare Cores PCIe 2 PHY for UMC 40-nm LP 1.1/2.5 V Databook ( PDF )
Download:	PCIe-20-PHY_UMC_40LP_x1
Product Code:	7326-0