17³Ô¹Ï Universal DDR Protocol Controller (uPCTL)
The 17³Ô¹Ï Universal DDR Protocol Controller (uPCTL) serves the memory control needs of applications with simple transactions that do not require an internal scheduler. The streamlined command based low-latency native interface (NIF) also enables the uPCTL to be integrated with a custom application specific scheduler.
The uPCTL is a bridge between a system-on-chip (SoC) application bus and a PHY for a DDR SDRAM, such as the 17³Ô¹Ï DDR PHYs. The uPCTL and the DDR PHY together handle the details of the DDR protocol, allowing the application to access memory via simple on-chip bus read/write requests.
The uPCTL connects to DDR PHYs via a DFI 2.1 interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface.
17³Ô¹Ï Universal DDR Memory and Protocol Controllers Datasheet
- For new designs or for designs with higher speed requirements and greater RAS features, consider the Enhanced Universal DDR Protocol Controller (uPCTL2) or Enhanced Universal DDR Memory Controller (uMCTL2)
- Join your own scheduler to a single-port enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, LPDDR/Mobile DDR, LPDDR2 and LPDDR3 SDRAMs
- DFI 2.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
- Data rates up to 2133 Mbps in 1:2 frequency ratio, using a 533 MHz controller clock and 1066 MHz memory clock (dependent on process)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using a 800 MHz controller clock and 800 MHz memory clock (dependent on process)