17³Ô¹Ï ARC-V RMX-100 Processor IP
The 17³Ô¹Ï ARC-V? RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V RMX-100 processors are based on the RISC-V instruction set architecture (ISA) and feature a balanced 3-stage Harvard architecture pipeline that provides sufficient throughput. The ARC-V RMX-100 features up to 64KB of level 1 (L1) instruction cache and up to 2MB each of closely coupled instruction and data memories (CCM).
To enable easy software development, the ARC MetaWare Development Toolkit features a rich software library. The ARC-V RMX-100 processors maintain the high code density and offer excellent performance within a very small footprint.
To maximize PPA of ARC-V RMX Processor-based designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.
17³Ô¹Ï ARC-V RMX-100 Block Diagram
17³Ô¹Ï ARC-V RMX-100 Series Datasheet
- Family of 32-bit RISC processors for ultra-low power embedded applications
- Based on the RISC-V ISA, RV32I and RV32E options leveraging standard 32-bit protocols (and extensions)
- Easy programming support with MetaWare C/C++ Compiler
- High degree of configurability
- Support for custom instructions
- Support for up to 2 MB of closely coupled memory and direct mapping of peripherals
- Native Arm AMBA? AHB?, AHBLite? and AXI interfaces
- Optional single and multicycle multiplier
- ECC/Parity support
- RISC-V AIA compatible interrupt handling architecture supporting up to 1023 direct message or wired interrupts
- Advanced Platform Level Interrupt Controller (APLIC) with low latency network
- N-Trace real-time trace debugging features