2025-04-11 07:45:56
17³Ô¹Ï 112G Ethernet PHY IP, an integral part of 17³Ô¹Ï' 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), very short reach (VSR) electrical channels and CEI-112G-Linear, and CEI-112G-XSR+ optical interfaces.
The 112G LR-Max PHY surpasses the performance targets of 112G-LR specification further extending channel reach in High Performance Compute applications.
The silicon-proven IP enables up to 800GbE hyperscale data center, networking, AI, pluggable optical module and Ethernet switch SoCs requiring high bandwidth and low latency.
17³Ô¹Ï 112G LR-Max PHY
Using leading-edge analog mixed-signal design and advanced digital signal processing technologies, the 112G LR-Max PHY IP provides additional margins to the CEI-112G LR specification and provides three orders of magnitude better bit error rate compared to the spec for 45dB channels.
17³Ô¹Ï 112G LR-Max TX Exceeds IEEE & OIF Jitter Specs with Symmetrical Eyes with Excellent Horizontal & Vertical Opening
17³Ô¹Ï 112G LR PHY
The power efficient PHY offers orders of magnitude better BER performance for Long Reach chip to chip channels with two connecters and multiple media. The PHYs¡¯ flexible layout maximizes bandwidth per die-edge by allowing the placement of square macros in a multi-row structure and along all edges of the die. Support for the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, and independent, per-lane data rates allows ultimate flexibility to address a broad range of protocols and applications.
17³Ô¹Ï 112G VSR PHY
Architected for very short reach chip-to-chip or chip-to-module electrical channels, the ultra-low power 112G VSR PHY enables power efficient pluggable and near packaged 400GbE/800GbE electro-optical interfaces.
Combined with 17³Ô¹Ï' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, 17³Ô¹Ï provides a comprehensive 112G Ethernet PHY IP products for fast and reliable SoC integration.
17³Ô¹Ï 112G Ethernet PHY IP Datasheet
17³Ô¹Ï 112G Ethernet PHY IP for Very Short Reach
Highlights
Products
Downloads and Documentation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
- Provides comprehensive 200G/400G/800G solution with routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis
- LR, MR and VSR: DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
- LR, MR and VSR: Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
- High-performance receive equalization supporting required channel loss
- Continuous calibration and adaptation (CCA) algorithms provide robust performance across process, voltage, and temperature variations
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
| 112G Ethernet LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N6 x4, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation | STARs |
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| 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation | STARs |
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| 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation | STARs |
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| 112G VSR PHY, TSMC N3P x2, North/South (vertical) poly orientation | STARs |
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| 112G VSR PHY, TSMC N5 x2, North/South (vertical) poly orientation | STARs |
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| 112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation | STARs |
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| 128G PHY, SS SF2P X4, North/South (vertical) poly orientation | STARs |
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| 128G PHY, SS SF4X X4, North/South (vertical) poly orientation | STARs |
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| 128G PHY, TSMC N3P X1, North/South (vertical) poly orientation | STARs |
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| 128G PHY, TSMC N3P X2, North/South (vertical) poly orientation | STARs |
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| 128G PHY, TSMC N3P X4, North/South (vertical) poly orientation | STARs |
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| 128G PHY, TSMC N5 X4, North/South (vertical) poly orientation | STARs |
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| Description: |
112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc5ff_x4ns |
| Version: |
3.07a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML )
17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF | HTML )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databook DesignWare? Cores Ethernet 112G PHY x4 for TSMC 5FF Databook (PHY Version: 3.07a) ( PDF | HTML )
Datasheet 17³Ô¹Ï 112G Ethernet PHY IP Datasheet ( PDF )
Reference Manual DesignWare? Cores Ethernet 112G PHY x4 for TSMC 5FF Reference Manual (PHY Version: 3.07a) ( PDF | HTML )
Release Notes DesignWare? Cores Ethernet 112G PHY x4 for TSMC 5FF Release Notes (PHY Version: 3.07a) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc5ff_x4ns |
| Product Code: |
E409-0 |
| Description: |
112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc6ff_x1ns |
| Version: |
3.05a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databook 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 6FF Databook (PHY Version: 3.05a) ( PDF | HTML )
Reference Manual 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 6FF Reference Manual (PHY Version: 3.05a) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 6FF Release Notes (PHY Version: 3.05a) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc6ff_x1ns |
| Product Code: |
E404-0 |
| Description: |
112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc6ff_x2ns |
| Version: |
3.05a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databook 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 6FF Databook (PHY Version: 3.05a) ( PDF | HTML )
Reference Manual 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 6FF Reference Manual (PHY Version: 3.05a) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 6FF Release Notes (PHY Version: 3.05a) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc6ff_x2ns |
| Product Code: |
E405-0 |
| Description: |
112G Ethernet PHY, TSMC N6 x4, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc6ff_x4ns |
| Version: |
3.05a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF | HTML )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databook 17³Ô¹Ï PHY IP Ethernet 112G PHY x4 for TSMC 6FF Databook (PHY Version: 3.05a) ( PDF | HTML )
Reference Manual 17³Ô¹Ï PHY IP Ethernet 112G PHY x4 for TSMC 6FF Reference Manual (PHY Version: 3.05a) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Ethernet 112G PHY x4 for TSMC 6FF Release Notes (PHY Version: 3.05a) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc6ff_x4ns |
| Description: |
112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc7ff_x1ns |
| Version: |
3.04b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databooks 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Databook (PHY Version: 3.04a) ( PDF | HTML )
17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Databook (PHY Version: 3.04b) ( PDF | HTML )
Reference Manuals 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Reference Manual (PHY Version: 3.04a) ( PDF | HTML )
17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Reference Manual (PHY Version: 3.04b) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Release Notes (PHY Version: 3.04a) ( TEXT )
17³Ô¹Ï PHY IP Ethernet 112G PHY x1 for TSMC 7FF Release Notes (PHY Version: 3.04b) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc7ff_x1ns |
| Product Code: |
E401-0 |
| Description: |
112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation |
| Name: |
dwc_112g_ethernet_phy_tsmc7ff_x2ns |
| Version: |
3.04b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP 112G Ethernet PHY Integration Review Checklist (Doc Version: 1.11a) ( PDF )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 2.00a) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES 112G Ethernet PHY ATE Testbench (Doc Version: 1.00a) ( PDF | HTML )
Databooks 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Databook (PHY Version: 3.04a) ( PDF | HTML )
17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Databook (PHY Version: 3.04b) ( PDF | HTML )
Reference Manuals 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Reference Manual (PHY Version: 3.04a) ( PDF | HTML )
17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Reference Manual (PHY Version: 3.04b) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Release Notes (PHY Version: 3.04a) ( TEXT )
17³Ô¹Ï PHY IP Ethernet 112G PHY x2 for TSMC 7FF Release Notes (PHY Version: 3.04b) ( TEXT )
|
| Download: |
dwc_112g_ethernet_phy_tsmc7ff_x2ns |
| Product Code: |
E402-0 |
| Description: |
112G PHY, TSMC N7 x4, North/South (vertical) poly orientation |
| Name: |
dwc_112g_phy_tsmc7ff_x4ns |
| Version: |
3.04a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Databooks 17³Ô¹Ï PHY IP Multi-Protocol 112G PHY x4 for TSMC 7FF (PHY Version: 3.04a) ( PDF | HTML )
17³Ô¹Ï PHY IP Multi-Protocol 112G PHY x4 for TSMC 7FF Reference Manual (PHY Version: 3.04a) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP Multi-Protocol 112G PHY x4 for TSMC 7FF Release Notes (PHY Version: 3.04a) ( TEXT )
|
| Download: |
dwc_112g_phy_tsmc7ff_x4ns |
| Product Code: |
F913-0 |
| Description: |
112G VSR PHY, TSMC N5 x2, North/South (vertical) poly orientation |
| Name: |
dwc_112g_vsr_phy_tsmc5ff_x2ns |
| Version: |
1.02a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes 17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.10a; VSR PHY) ( PDF | HTML )
Databook DesignWare? Cores VSR 112G PHY for TSMC 5FF Databook (PHY Version: 1.02a) ( PDF | HTML )
Reference Manual DesignWare? Cores VSR 112G PHY for TSMC 5FF Reference Manual (PHY Version: 1.02a) ( PDF | HTML )
Release Notes DesignWare? Cores VSR 112G PHY for TSMC 5FF Release Notes (PHY Version: 1.02a) ( TEXT )
|
| Download: |
dwc_112g_vsr_phy_tsmc5ff_x2ns |
| Product Code: |
H346-0 |
| Description: |
112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation |
| Name: |
dwc_112g_vsr_phy_tsmc5ff_x8ns |
| Version: |
1.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF | HTML )
17³Ô¹Ï PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.10a; VSR PHY) ( PDF | HTML )
17³Ô¹Ï PHY IP SERDES E112G VSR PHY ATE Testbench (Doc Version: 1.02a) ( PDF | HTML )
17³Ô¹Ï PHY IP VSR 112G PHY Firmware (Doc Version: 1.05a) ( PDF | HTML )
Databook 17³Ô¹Ï PHY IP VSR 112G PHY for TSMC 5FF Databook (PHY Version: 1.03a) ( PDF | HTML )
Reference Manual 17³Ô¹Ï PHY IP VSR 112G PHY for TSMC 5FF Reference Manual (PHY Version: 1.03a) ( PDF | HTML )
Release Notes 17³Ô¹Ï PHY IP VSR 112G PHY for TSMC 5FF Release Notes (PHY Version: 1.03a) ( TEXT )
User Guide 17³Ô¹Ï PHY IP VSR 112G PHY Customer Testbench (Doc Version: 1.04a) ( PDF | HTML )
|
| Download: |
dwc_112g_vsr_phy_tsmc5ff_x8ns |
| Product Code: |
H204-0 |
