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Functional Verification Datasheet Download

17³Ô¹Ï VC Verification IP

17³Ô¹Ï VC Verification IP (VIP), source code Test Suite and Verification Subsystem 17³Ô¹Ï provide access to 90+ industry protocols, interfaces, memories, and subsystems required to verify IP, subsystem and SoC designs. VIP, Test Suites and Subsystems provide a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of IP, subsystems and SoC designs. 17³Ô¹Ï VIP solutions are based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affect performance and ease-of-use. The VIP solutions can be integrated, configured, and customized with minimal effort, enabling designers to easily expand usage and meet organizations requirements.

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